Efficient Design and Implementation of DFA Based Pattern Matching onHardware
Pattern matching is a crucial task in several critical network
services such as intrusion detection. In this paper we present an
efficient implementation of the DFA with optimized area and
optimized memory by the introduction of state minimization. By
using minimized DFA the clock frequency reduces to 40% of the
original and the area also reduces to 30%. This optimized
architecture of DFA is simulated and synthesized using VHDL
on the Xilinx ISE 12.4.
Keywords: String Matching, DFA, VHDL.
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ABOUT THE AUTHORS
Aakanksha Pandey
M Tech Information Security, Maulana Azad National Institute of Technology Bhopal, Madhya Pradesh 462003, India
Dr. Nilay Khare
Faculty of Computer Science Engineering, Maulana Azad National Institute of Technology Bhopal, Madhya Pradesh 462003, India
Akhtar Rasool
Faculty of Computer Science Engineering, Maulana Azad National Institute of Technology Bhopal, Madhya Pradesh 462003, India
Aakanksha Pandey
M Tech Information Security, Maulana Azad National Institute of Technology Bhopal, Madhya Pradesh 462003, India
Dr. Nilay Khare
Faculty of Computer Science Engineering, Maulana Azad National Institute of Technology Bhopal, Madhya Pradesh 462003, India
Akhtar Rasool
Faculty of Computer Science Engineering, Maulana Azad National Institute of Technology Bhopal, Madhya Pradesh 462003, India
