International Journal of Computer Science Issues

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High resolution analog to digital converters (ADCs) have been based on self–calibrated successive approximation technique, because it uses a single comparator and consumes less power. Unfortunately successive approximation technique requires N comparisons to convert N bit digital code from an analog sample. This makes successive approximation ADCs unsuitable for high speed applications. This paper demonstrates a simple technique to enhance speed of successive approximation ADCs that require as few as N-5 comparisons for N bit conversion. This technique optimizes the number of comparator requirements while increasing conversion speed by 62.5% for 8-bit resolution. In our approach, the analog input range is partitioned into 32 quantization cells, separated by 31 boundary points. A 5-bit binary code 00000 to 11111 is assigned to each cell. A normal successive approximation converter requires 8 comparisons for 8-bit quantization, while our proposed technique reduces number of comparison requirements to only 3 for 8 bit conversion. Therefore this technique is best suitable when high speed combined with high resolution is required. Result of 8-bit prototype is presented.