Several AES Variants under VHDL language In FPGA
This paper provides four different architectures for encrypting and decrypting 128 bit information via the AES. The encryption algorithm includes the Key Expansion module which generates Key for all iterations on the fly, Double AEStwo-key triple AES, AESX and AES-EXE. These architectures are implemented and studied in Altera Cyclone III and STRATIX Family devices.
Keywords: double AES , Triple AES,AESx,AES-exe, VHDL code.
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ABOUT THE AUTHORS
Sliman Arrag
Professor of secondary education qualifying. Follow Phd in Department of Electronics and treatment of information, from UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco.
Abdellatif Hamdoun
Professor in Electronics Engineering from UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco, PES degree.
Abderrahim Tragha
Professor in Mathematics from UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco, PES degree.
Salah Eddine Khamlich
Professor of practical work from UNIVERSITE HASSAN II MOHAMMEDIA.follow Phd in Electronics and treatment of information.
Sliman Arrag
Professor of secondary education qualifying. Follow Phd in Department of Electronics and treatment of information, from UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco.
Abdellatif Hamdoun
Professor in Electronics Engineering from UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco, PES degree.
Abderrahim Tragha
Professor in Mathematics from UNIVERSITE HASSAN II MOHAMMEDIA, Casablanca, Morocco, PES degree.
Salah Eddine Khamlich
Professor of practical work from UNIVERSITE HASSAN II MOHAMMEDIA.follow Phd in Electronics and treatment of information.
