Optimization of Power Consumption in VLSI Circuit
Space, power consumption and speed are major design issues in VLSI circuit. The design component has conflicting affect on overall performance of circuits. An optimization of power dissipation can be achieved by compromising various components. Power consumption in VLSI circuit (like in multipliers) is also data dependent. In this paper attempt has been made to test different design methods and propose a modular approach for optimizing power consumption. It is found that algorithm based design reduce gate switching activity considerably and as result power consumption in multiplier is reduced.
Keywords: Genetic Algorithm, Booth Multiplication, Power Optimization
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