Friday 26th of April 2024
 

Efficient Circuit Configuration for Enhancing Resolution of 8-bit flash Analog to Digital Convertor


Gururaj Balikatti, R.M Vani and P.V. Hunagund

The need constantly exists for converters with higher resolution, faster conversion speeds and lower power dissipation. High speed analog to digital converters (ADCs) have been based on flash architecture, because all comparators sample the analog input voltage simultaneously, this ADC is thus inherently fast. Unfortunately flash ADC requires 2N - 1 comparators to convert N bit digital code from an analog sample. This makes flash ADCs unsuitable for high resolution applications. The focus of this paper is on efficient circuit configuration to enhance resolution of available 8-bit flash ADC, while maintaining number of comparators only 256 for 12 bit conversion. This technique optimizes the number of comparator requirements. In this approach, an 8-bit flash ADC partitions the analog input range into 256 quantization cells, separated by 255 boundary points. An 8-bit binary code 00000000 to 11111111 is assigned to each cell. The Microcontroller decides within which cell the input sample lies and assigns a 12-bit binary center code 000000000000 to 111111111111 according to the cell value. The exact 12-bit digital code is obtained by successive approximation technique. In this paper the focus will be on all-around efficient circuit for enhancing resolution of 8-bit Flash ADC. It is shown that by adopting this configuration, we can obtain 12-bit digital data just using 256 comparators. Therefore this technique is best suitable when high speed combined with high resolution is required. An experimental prototype of proposed 12-bit ADC was implemented using Philips P89V51RD2BN Microcontroller. Use of Microcontroller has greatly reduced the hardware requirement and cost. An ADC result of 12-bit prototype is presented. The results show that the ADC exhibits a maximum DNL of 0.52LSB and a maximum INL of 0.55LSB.

Keywords: Flash ADC, Microcontroller, DAC, Sample and Hold. Successive approximation.

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ABOUT THE AUTHORS

Gururaj Balikatti
Gururaj Balikatti is an Associate Professor & Head of the Department of Electronics, Maharani’s Science College for Women, Bangalore, India. He obtained his M.Sc. and M.Phil. in Applied Electronics from Gulbarga University, Gulbarga. India in 1989 and 1990. Presently pursuing Ph.D in Applied Electronics from Gulbarga University, Gulbarga. India. He is the author of one international Journal, one international, three National level and six state level conference papers. His research interest includes embedded controllers.

R.M Vani
Vani R M received P.hD in Applied Electronics from Gulbarga University, Gulbarga, India. She is working as Head, USIC, Gulbarga University, Gulbarga. She has more than 26 research publications in national and international journals. Also she presented the research papers in national and international conferences in India and abroad. Her area of interest are microwave antennas, PC based instrumentation, embedded controllers and wireless communication.

P.V. Hunagund
Hunagund P V received P.hD in Applied Electronics from Gulbarga University, Gulbarga, India. He is working as Professor of Applied Electronics, Gulbarga University, Gulbarga. he has more than 50 research publications in national and international journals, More than 75 research publications international symposium/conference and more than 51 research publications in national symposium/conference Also presented the research papers in national and international conferences in India and abroad.


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