Friday 26th of April 2024
 

Design and Implementation of Memory-less Forbidden Transition Free Crosstalk Avoidance CODECs for On-Chip Buses


J.Venkateswara Rao and P.Sudhakara Rao

Recently, reducing crosstalk noise delay is an important issue in VLSI design. As circuit geometries become smaller, wire interconnections become closer together and taller, thus increasing the cross-coupling capacitance between nets. At the same time, parasitic capacitance to the substrate becomes less as interconnections become narrower, and cell delays are reduced as transistors become smaller. In this work, we present a CODEC design for the forbidden transition free crosstalk avoidance CODEC. Our mapping and coding scheme is based on the Binary number system. In this paper, we investigate and propose a bus forbidden transition free CODECs for reducing bus delay and our experimental results show that the proposed CODEC complexity is orders of magnitude better compared to the existing techniques. Compared to the best existing approaches, we achieved a 3 times faster design and improvement in logic complexity.

Keywords: Crosstalk, Crosstalk Avoidance Codes, Forbidden Transition Free, Encoding, System on Chip, Parasitic, Coupling Capacitance, Deep-submicron.

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ABOUT THE AUTHORS

J.Venkateswara Rao
J.Venkateswara Rao received B.Tech Degree from, VRSEC, Nagarjuna University, Guntur, in 2000. M.Tech. Degree from NITW, Warangal, India in 2003, pursuing Ph.D in the Department of Electronics and Communication Engineering, JNT University, Hyderabad, INDIA. Currently he is working as Associate Professor in the Department of Electronics and communication Engineering, VITS, Hyderabad, INDIA, His research interest includes on chip crosstalk noise reduction in VLSI Circuits. He published 4 papers on “on-chip crosstalk noise reduction in VLSI circuits” in international journals and international conferences.

P.Sudhakara Rao
Dr.P.Sudhakara Rao Completed Ph.D., Information and Communication Engineering from Anna University, India, Masters in Electronics and Communication Engineering from Anna University, India, Bachelors in Electronics and Communication Engineering from Mysore University, India. Worked as deputy Director, “Central Electronics Engineering Research Institute centre, India” for over 25 years, 2 years as Vice-president, “Sieger Spintech Equipments Ltd., India”, established an electronic department for the development of electronic systems for nearly 2 years. Presently working with Vignan Institute of Technology and Science, Nalgonda District, AP, INDIA as DEAN R&D, HOD ECE. He has one patent and 55 technical publications/ conference papers to his credit. Conducted many international and national conferences as chairman.


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