Tuesday 23rd of April 2024
 

Restructuring adders for Binary/BCD addition/subtraction under the condition of no sign bit in BCD format


Tara Tavakoli, Reza Talebiyan, Nastaran Parvin and Safiyeh Nikkhah Sani

This paper presents a new architecture for binary / BCD addition / subtraction to accelerate the operations and reduce delays in both signed numbers and unsigned numbers. Adding numbers in binary or BCD is one of the most important mathematical operations in digital systems. Various numbers of structures have been proposed to apply the BCD adder and subtraction, and the last structure presented in this article for BCD adder /subtraction of numbers assumes these numbers without any signs. Some articles have been used for some parts of this paper; and these articles, despite their strengths and advantages, contain some problems with their final computing. This paper has solved the problems in the final computing EOP. So, a new structure for addition / subtraction of BCD is presented if the sign bit is not taken into account and work properly.

Keywords: adder, subtractor, signbit, condition, Restructuring

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ABOUT THE AUTHORS

Tara Tavakoli
Tara Tavakoli, born in Mashhad, Iran on September 14, 1987. Got her Associates degree of Software Engineering on September 2008 from Khayyam University of Mashhad, Iran; her Bachelors degree of Hardware Engineering on September 2011 from Khavaran University of Mashhad, Iran; and her Masters degree of Architecture of Computer on September 2014 from Imam Reza International University of Mashhad, Iran. Ms. Tavakkoli is not involved nor have any membership in any association or society currently.

Reza Talebiyan
individual

Nastaran Parvin
individual

Safiyeh Nikkhah Sani
individual


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