Optimization of multi-channel HDLC protocol transceiver using Verilog
To transmit and receive data at high speed in any network without any error a protocol is required. HDLC protocol of layer-2 of OSI model which is most suitable for bit oriented packet transmission mode is discussed in this article. HDLC protocol was designed with two full-duplex channels on the principle of Top-Down design. Verilog HDL coding of the design is done using Xilinx ISE and is implemented on Vertex FPGA, The design has been verified through simulation and synthesis of the existing and proposed design.
Keywords: 4zriqdrs460tmyIJCSI-2012-9-1-1249856isc02knp
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ABOUT THE AUTHORS
Harpreet Singh
Lect. (Electronics & Communication) , Govt. Polytechnic College, Amritsar, Punjab, India
Navneet Kaur
Lect. (Information Technology) , Govt. Polytechnic College, Amritsar, Punjab, India
Vinay Chopra
Assistant Professor CSE, DAVIET, Jalandhar, Punjab, India
Amardeep Singh
Associate Professor, University College of Engg., Punjabi University , Patiala, Punjab, India
Harpreet Singh
Lect. (Electronics & Communication) , Govt. Polytechnic College, Amritsar, Punjab, India
Navneet Kaur
Lect. (Information Technology) , Govt. Polytechnic College, Amritsar, Punjab, India
Vinay Chopra
Assistant Professor CSE, DAVIET, Jalandhar, Punjab, India
Amardeep Singh
Associate Professor, University College of Engg., Punjabi University , Patiala, Punjab, India
