Thursday 28th of March 2024
 

OMP2HMPP: Compiler Framework for Energy-Performance Trade-off Analysis of Automatically Generated Codes


Albert Saa-Garriga, David Castells-Rufas and Jordi Carrabina

We present OMP2HMPP, a tool that, in a first step, automatically translates OpenMP code into various possible transformations of HMPP. In a second step OMP2HMPP executes all variants to obtain the performance and power consumption of each transformation. The resulting trade-off can be used to choose the more convenient version. After running the tool on a set of codes from the Polybench benchmark we show that the best automatic transformation is equivalent to a manual one done by an expert. Compared with original OpenMP code running in 2 quad-core processors we obtain an average speed-up of 31 and 5.86 factor in operations per watt.

Keywords: Source to source compiler, GPGPU, HMPP, parallel computing, program understanding, compiler optimization.

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ABOUT THE AUTHORS

Albert Saa-Garriga
Albert Saà-Garriga received his B.Sc. degree in Computer Science and M.Sc. degree in Computer Vision and Artificial Intelligence from Universitat Autònoma de Barcelona (UAB), Bellaterra, Spain. He is currently at CEPHIS (Hardware-Software Prototypes and Solutions Lab), research center at the UAB, where he is doing his Ph.D. studies. His main research interests include parallel computing, source to source compilers and computer vision systems.

David Castells-Rufas
David Castells-Rufas received his B.Sc. degree in Computer Science from Universitat Autònoma de Barcelona. He holds a M.Sc. in Research in Microelectronics from Universitat Autònoma de Barcelona. He is currently the head of the Embedded Systems unit at CAIAC Research Centre at Universitat Autònoma de Barcelona (UAB), where he is doing his Ph.D. studies. His primary research interests include parallel computing, Network-on-Chip Based Multiprocessor Systems, and parallel programming models. He is also associate lecturer in the Microelectronics department of the same university.

Jordi Carrabina
Jordi Carrabina leads CAIAC Research Centre at Universitat Autònoma de Barcelona (Spain), member of Catalan IT network TECNIO. He received his PhD degree from Universitat Autònoma de Barcelona. His main interests are Microelectronic Systems oriented to Embedded Platform-based Design using System Level Design Methodologies using SoC/NoC Architectures and Printed Microelectronics Technologies in the Ambient Intelligence Domain. He is a Prof. T. at Universitat Autònoma de Barcelona where is Teaching EE and CS at the Engineering School and in the MA of Micro & Nanoelectronics Engineering and Multimedia technologies, at UAB and Embedded Systems at UPV-EHU.


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