Multi FPGA Based Novel Reconfigurable Hybrid Architecture for High Performance Computing
The growth of the verticals depending on the
reconfigurable computing has been very fast. Satellite
systems, land rovers, rocket launchers and other heavy
duty high performance systems are making use of
reconfigurable processors. However, still these processors
are not able to provide for the strict hard real time
deadlines required. The reason behind is the flexibility of
being reconfigured, the delay in the transfer of signals and
the time required to reconfigure the part of FPGA based
multiprocessors is slightly higher. Thus we are proposing a
Multi FPGA based Novel Reconfigurable hybrid
architecture which provides for a lesser delay, more
reliability and a higher throughput. This system
architecture has been developed with the intent of reducing
the dynamic decision making so as to reduce the run time
and also by minimising the number of context switching
operations by providing more than one FPGA processors.
So that the need for context switching in normal
circumstances is reduced to zero and is only required in
case a failure occurs in the system.
Keywords: Reconfigurable Computing, FPGA, Hybrid Architecture, RPU, Context switching
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