Thursday 28th of March 2024
 

Modify the uCS-51 with Vector Instructions


Assem Badr, Abdelmoneim M. Fouda and Abdelsamie Kodb

Computer architects have always strived to increase the overall speed of processing for the CPUs. utilizing a reserved unused machine code \A5H\, we can expands the tradition instruction set architecture (ISA) for the Cs-51 family, in this paper we introduce modification of internal architecture for the Cs-51 and their ISA to improve the overall C performance, specifically we will introduce two innovated vector instructions for the Cs-51 family. The two vector instructions exploiting the data manipulation. The first instruction is to transfer a block of data from specific memory locations to any other memory locations simultaneously, while the other vector instruction is to obtain the minimum data byte value within a block of data bytes. Also we will supply the modified C with pipeline technique for decreasing the total execution time. Such development improves the total performance of the C including execution time, and storage ratio.

Keywords: µCS-51, ISA, Vector instruction, VHDL, pipeline, Amdahls law, Iron law.

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ABOUT THE AUTHORS

Assem Badr
Computer Eng. Department, Modern Academy for Engineering & Technology Cairo, Egypt

Abdelmoneim M. Fouda
Computer Eng. Department, Modern Academy for Engineering & Technology Cairo, Egypt

Abdelsamie Kodb
Electrical Eng. Department, Faculty of Engineering, Al-Azhar University Cairo, Egypt


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