Friday 29th of March 2024
 

Low Power GALS Interface Implementation with Stretchable Clocking Scheme


Anju C and Kirti S Pande

Complex SoC imply the seamless integration of numerous IPs performing different functions and operating at different clock frequencies. The integration of several heterogeneous components into a single system gives rise to new challenges. Major issue includes controlling the clock frequencies of the different modules. As chips become faster and larger, designers face significant challenges including global clock distribution and power dissipation. In-order to achieve global synchronization with high performance and low power conception globally asynchronous locally synchronous (GALS) method is used. In GALS, local modules can operate with their own clock and the entire module is communicating asynchronously. In this paper we implemented a low power GALS interface with stretchable clocking scheme in verilog HDL and compare the dynamic power of the interface with and without stretchable clocking with Synopsys Design Compiler.

Keywords: Globally asynchronous locally synchronous, System on Chip, Stretchable clocking scheme, Asynchronous wrapper

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ABOUT THE AUTHORS

Anju C
Anju C received her B.Tech degree in Electronics and Communication from Cochin University of Science and Technology, Kerala, India in 2009 and currently pursuing M.Tech in VLSI Design from Amrita Vishwa Vidyapeetham. Her research interests include VLSI design and system on chip.

Kirti S Pande
Kirti S Pande She graduated from Nagpur University in 2001. She completed post graduation from Amrita Vishwa Vidyapeetham in 2010. She worked as a lecturer at various universities like Nanded University, Visvesvaraya Technological University. Presently she is working as an Asst.Professor at Amrita Vishwa Vidyapeetham and has been engaged with research in VLSI design, processor based design and FSM based digital design.


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