Thursday 21st of September 2017
 

Heuristics for Routing and Spiral Run-time taskMapping in NoC-based Heterogeneous MPSOCs


Mohammed Kamel Benhaoua, Abbou El Hassen Benyamina and Pierre Boulet

MultiProcessor Systems on Chip (MPSoC) has emerged as a solution to adress the incremental Computational requirements for future applications. The Network-On-Chip (NoC) has been introduced as a power-efficient, scalable inter communication, interconnection mechanism between processors. One important phase in architectural exploration in NOC-based MPSOC is the mapping. The application and architectural are represented by processing model, application task graph and architectural graph respectively. Mapping parallelized tasks of applications onto these MPSoCs can be done either at designtime (static) or at run-time (dynamic). Static mapping strategies find the best placement of tasks at design-time and hence these are not suitable for dynamic workload and seem incapable of runtime resource management. The number of tasks or applications executing in MPSoC platform can exceed the available resources, requiring efficient run-time mapping strategies to meet with this constraints. This paper describes a new Spiral Dynamic Task Mapping heuristic for mapping applications onto NoC-based Heterogeneous MPSoC. This heuristic is based on packing strategy and routing Algorithm proposed also in this paper. Heuristic try to map the tasks of an application in a clustering region to reduce the communication overhead between the communicating tasks. The heuristic proposed in this paper attempts to map the tasks of an applications that are most related to each other in spiral manner and to find the best possible path load that minimizes the communication overhead. In this context, we have realized a simulation environment for experimental evaluations to map applications with varying number of tasks onto an 8x8 NOC-based Heterogeneous MPSOCs platform, we demonstrate that the new mapping heuristics with the new routing algorithm proposed are capable of reducing the total execution time and energy consumption of applications when compared to state-ofthe- art run-time mapping heuristics reported in the literature.

Keywords: MultiProcessor System on Chip (MPSoC), Network on Chip (NoC), Heterogeneous architectures, Run-time mapping Heuristics, Routing Algorithm.

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ABOUT THE AUTHORS

Mohammed Kamel Benhaoua
received his Bachelor degree in computer science, Oran University, Algeria, in 2005. received his Magister degree in computer science, Oran University, Algeria, in 2009. Currently, he is working with Mascara University, as a research professor and student towards the completion of his PhD. His research interests include NoC-based MPSoC design, run-time mapping algorithms.

Abbou El Hassen Benyamina
received his Ph.D. degree in Computer Science in 2008 from University of Oran (Algeria), He is professor at the ORAN university (Algeria). His research works include parallel processing, optimization, design space exploration and Model Driven Engineering with the special focus on real-time and embedded systems.

Pierre Boulet
received his Ph.D. degree in Computer Science in 1996 from University of Lyon, He was assistant professor at the university Lille 1 from September 1998 to August 2002, and then became a researcher at INRIA Futurs from September 2002 to August 2003. Since September 2003, he is a full professor at the university Lille 1. His research works include parallel processing, optimization, design space exploration and Model Driven Engineering with the special focus on real-time and embedded systems.


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