FinFET Architecture Analysis and Fabrication Mechanism
In view of difficulties of the planar MOSFET technology to get the acceptable gate control over the channel FinFET technology based on multiple gate devices is better technology option for further shrinking the size of the planar MOSFET [1]. For double gate SOI- MOSFET the gates control the channel created between source and drain terminal effectively. So the several short channel effects like DIBL, subthreshold swing, gate leakage current etc. without increasing the carrier concentration into the channel.
This paper mainly deals with detail description about the DG MOSFET structure and its particular type named as FinFET technology and its fabrication mechanism is also described. Below the 50nm technology FinFET has better controlling over the several short channel effects.
In section one the introduction is given, section two describe the Evaluation from previous technology, section three describe the DG MOSFET structure and its type, section four describe the FinFET technology, section five describe the fabrication mechanism of the FinFET technology and finally conclusions given in section six.
Keywords: CMOS scaling, DG MOSFET, FinFET, Short Channel Effect, SOI Technology
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ABOUT THE AUTHORS
Sarman K Hadia
Sarman K. Hadia is Associate Professor in Electronics and Communication Department at Charotar University of Science and Technology, Changa He is presently Ph.D. pursuing in VLSI Technology. His research interests are Microelectronics and optimization techniques.
, Rohit R. Patel
Rohit R. Patel is M.Tech. Student of C.S. Patel Institute of Technology, CHARUSAT, Changa in Communication system Engineering. He had completed his Bachelor of Engineering Degree from Vishwakarma Government Engineering Collage, Chandkheda, Gandhinagar, India.
Dr. Yogesh P. Kosta
Yogesh P. Kosta is an SCPM from Stanford University, California, USA. He did his M. Tech. in Microwave Electronics from Delhi University Delhi, and his Ph.D. in Electronics and Telecommunication. He is a member of IETE and IEEE. He worked as a scientist and designer at the Space Application Canter – ISRO Ahmedabad, and as a Sr. Designer at Teledyne USA. Presently he is Director of Marwadi Group of Institutions. His research areas are RF, Wireless Satellite Systems and Information Communications. He has guided several M. Tech students. At present, six research scholars are currently pursuing their Ph.D under his guidance. He has published many research papers and articles in referred journals and international conference proceedings.
Sarman K Hadia
Sarman K. Hadia is Associate Professor in Electronics and Communication Department at Charotar University of Science and Technology, Changa He is presently Ph.D. pursuing in VLSI Technology. His research interests are Microelectronics and optimization techniques.
, Rohit R. Patel
Rohit R. Patel is M.Tech. Student of C.S. Patel Institute of Technology, CHARUSAT, Changa in Communication system Engineering. He had completed his Bachelor of Engineering Degree from Vishwakarma Government Engineering Collage, Chandkheda, Gandhinagar, India.
Dr. Yogesh P. Kosta
Yogesh P. Kosta is an SCPM from Stanford University, California, USA. He did his M. Tech. in Microwave Electronics from Delhi University Delhi, and his Ph.D. in Electronics and Telecommunication. He is a member of IETE and IEEE. He worked as a scientist and designer at the Space Application Canter – ISRO Ahmedabad, and as a Sr. Designer at Teledyne USA. Presently he is Director of Marwadi Group of Institutions. His research areas are RF, Wireless Satellite Systems and Information Communications. He has guided several M. Tech students. At present, six research scholars are currently pursuing their Ph.D under his guidance. He has published many research papers and articles in referred journals and international conference proceedings.
