Friday 22nd of September 2017
 

Fault Tolerant Circuit Design Using Evolutionary Algorithms


Hui-Cong Wu

With the rapid development of semiconductor technology and the increasing proliferation of emission sources, digital circuits are frequently used in harsh electromagnetic environments. Electrostatic Discharge (ESD) interferences are gradually gaining prominence, resulting in performance degradations, malfunctions and disturbances in component or system level applications. Conventional solutions to such problem are shielding, filtering and grounding. This paper presents an evolvable hardware platform for the automated design and adaptation of a motor control circuit. The platform uses EHW to automate the configuration of FPGA dedicated to the implementation of the motor control circuit. The ability of the platform to adapt to certain number of faults was investigated through introducing single logic unit fault and multi-logic unit faults. Results show that the functionality of circuit can be recovered through evolution. It also shows that the placement of faulty affect the ability of GA to evolve correct circuit, and the evolutionary recovery ability of the circuit descends with the number of fault units increasing.

Keywords: Evolvable Hardware, Fault Tolerant, Motor Control Circuits

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ABOUT THE AUTHOR

Hui-Cong Wu
Hui-cong Wu get her doctor\'s degree from Shijiazhunag Mechanical Engineering College in 2007, She is an associate professor in Hebei University of Science & Technology. She visited The University of Birmingham, UK from 2009 to 2010. Her research interests include evolutionary computation, software engineering, data mining.


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