Fault Detection Scheme for AES Using Optimization for Mix Column
In this paper for existing concurrent structure independent fault detection schemes with new technique for the fault detection of sub bytes and inverse sub bytes using the relation between the input and output of the S-box, the formulation of mix column are implemented for AES, which results in the reduction of area coverage and power consumption along with the error coverage of greater than 99% of the existing scheme. The proposed scheme and existing scheme have been implemented on the most recent Xilinx Sparton FPGA, their area and power requirements are compared and it is proved that proposed technique makes the fault detection for AES efficient in terms of area coverage(in terms of gate count) and power consumption.
Keywords: AES(Advanced encryption standard), FPGA(Field programmable gate array), Galois field, Mix column
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ABOUT THE AUTHORS
H.K.Reshma Ramesh
H.K. Reshma Ramesh received the BE degree in electronics and communication engineering from Kuvempue university. She has total 9 years of teaching experience .She is currently working towards the M.Tech (By Research) degree at the department of Electronics and communication engineering, Anna University, Coimbatore. Her research interest includes secure cryptographic systems, Embedded applications and VLSI reliability.
N.Nagarajan
Nagarajan.N received his B.Tech and M.E. degree in Electronics Engineering at M.I.T Chennai. He received his Ph.D in faculty of I.C.E. from Anna University, Chennai. He is currently working as Dean, CSE, C.I.E.T, Coimbatore. His specialization includes optical, wireless Adhoc and sensor networks.
H.K.Reshma Ramesh
H.K. Reshma Ramesh received the BE degree in electronics and communication engineering from Kuvempue university. She has total 9 years of teaching experience .She is currently working towards the M.Tech (By Research) degree at the department of Electronics and communication engineering, Anna University, Coimbatore. Her research interest includes secure cryptographic systems, Embedded applications and VLSI reliability.
N.Nagarajan
Nagarajan.N received his B.Tech and M.E. degree in Electronics Engineering at M.I.T Chennai. He received his Ph.D in faculty of I.C.E. from Anna University, Chennai. He is currently working as Dean, CSE, C.I.E.T, Coimbatore. His specialization includes optical, wireless Adhoc and sensor networks.
