Friday 29th of March 2024
 

Development of MIL-STD-1553B Synthesizable IP Core for Avionic Applications


Enumala Srikrishna, P.H.S.T.Murthy and L.Madanmohan

MIL-STD-1553, Digital Time Division Command/Response Multiplex Data Bus, is a military standard (presently in revision B), which has become one of the basic tools being used today for integration of weapon systems. The standard describes the method of communication and the electrical interface requirements for subsystems connected to the data bus. The 1 Mbps serial communication bus is used to achieve aircraft avionic (MIL-STD-1553B) and stores management (MILSTD-1760B) integration. The standard defines four hardware elements. These are 1) The transmission media, 2) Remote terminals, 3) Bus controllers, 4) Bus monitors. The main objective of this paper is to develop an IP (Intellectual Property) core for the MIL-STD-1553 IC. This IP core can be used as bus monitors or remote terminals or bus monitors. The main advantage of this IP core is to provide small foot print, flexibility and reduce the cost of the system, as we can integrate this with other logic

Keywords: MIL-STD-1553 ,Bus controller,Bus monitor

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ABOUT THE AUTHORS

Enumala Srikrishna
Specialised in Verilog programming

P.H.S.T.Murthy
specialised in VLSI

L.Madanmohan
5 years industrial experiance


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