International Journal of Computer Science Issues

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This paper presents the design and analysis of a high efficiency, PWM (Pulse-Width-Modulation) Buck converters for mobile phone applications. The steady-state and average-value models for the proposed converter are developed and simulated. A practical design approach which aims at systematizing the procedure for the selection of the control parameters is introduced. The switching losses are reduced by using soft switching, additionally, a simple analog and digital form of the controller for practical realization is provided. It is found that this controller adopts a structure similar to the conventional PWM voltage mode controller. The proposed circuit uses a current-mode control and a voltage-to-pulse converter for the PWM. The circuit, fabricated using a 0.18-m CMOS technology, reaches a peak load regulation of 20 mV/V and line regulation of 0.5 mV/V at Current load equal 300 mA. The used 10H inductance and 22F capacitor and requires clock and Vref/Vramp input of 1,23V.