Design of a High Performance Reversible Multiplier
Reversible logic circuits are increasingly used in power minimization having applications such as low power CMOS design, optical information processing, DNA computing, bioinformatics, quantum computing and nanotechnology. The problem of minimizing the number of garbage outputs is an important issue in reversible logic design. In this paper we propose a new 44 universal reversible logic gate. The proposed reversible gate can be used to synthesize any given Boolean functions. The proposed reversible gate also can be used as a full adder circuit. In this paper we have used Peres gate and the proposed Modified HNG (MHNG) gate to construct the reversible fault tolerant multiplier circuit. We show that the proposed 44 reversible multiplier circuit has lower hardware complexity and it is much better and optimized in terms of number of reversible gates and number of garbage outputs with compared to the existing counterparts.
Keywords: Reversible logic circuit, reversible logic gates, reversible multiplier circuits, quantum computing, nanotechnology based systems.
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ABOUT THE AUTHORS
Md.Belayet Ali
He received his B.Sc degree in Computer Science and Engineering from Mawlana Bhashani Science and Tecgncehnology University, Santosh, Tangail, Bangladesh, in 2008. He is working as Lecturer in Department of Computer Science and Engieering at Mawlana Bhashani Science and Technology University (MBSTU), Santosh, Tangail, Bangladesh. He has 1 year experience of working in MBSTU. He has published 03(three) papers in national, international journals. His area of interest includes reversible logic synthesis, multi-valued reversible logic synthesis, network business security, cloud computing.
Hosna Ara Rahman
She is currently completing her B.Sc degree in Computer Science and Engineering at Mawlana Bhashani Science and Technology University, Santosh, Tsangail, Bangladesh. Her area of interest include reversible logic synthesis.
Md. Mizanur Rahman
He is currently completing his B.Sc degree in Computer Science and Engineering at Mawlana Bhashani Science and Technology University, Santosh, Tsangail, Bangladesh. His area of interest include reversible logic synthesis.
Md.Belayet Ali
He received his B.Sc degree in Computer Science and Engineering from Mawlana Bhashani Science and Tecgncehnology University, Santosh, Tangail, Bangladesh, in 2008. He is working as Lecturer in Department of Computer Science and Engieering at Mawlana Bhashani Science and Technology University (MBSTU), Santosh, Tangail, Bangladesh. He has 1 year experience of working in MBSTU. He has published 03(three) papers in national, international journals. His area of interest includes reversible logic synthesis, multi-valued reversible logic synthesis, network business security, cloud computing.
Hosna Ara Rahman
She is currently completing her B.Sc degree in Computer Science and Engineering at Mawlana Bhashani Science and Technology University, Santosh, Tsangail, Bangladesh. Her area of interest include reversible logic synthesis.
Md. Mizanur Rahman
He is currently completing his B.Sc degree in Computer Science and Engineering at Mawlana Bhashani Science and Technology University, Santosh, Tsangail, Bangladesh. His area of interest include reversible logic synthesis.