Saturday 20th of April 2024
 

CDMA Based Interconnect Mechanism for SOPC


V. Rajesh and P. Vijaya Kumar

The Network-on-chip (NoC) designs consisting of large pack of Intellectual Property (IP) blocks (cores) on the same silicon die is becoming technically possible nowadays. But, the communication between the IP Cores is the main issue in recent years. This paper presents the design of a Code Division Multiple Access (CDMA) based wrapper interconnect as a component of System on programmable chip (SOPC) builder to communicate between IP cores. In the proposal, only bus lines that carry address and data signals are CDMA coded. CDMA technology has better data integrity, channel continuity, channel isolation, and also mainly it reduces the no.of lines in the bus architecture for transmitting the data from master to slave.

Keywords: CDMA, On-Chip interconnects, SOPC, Shared Bus Architecture, Encoding, and Decoding, Custom component.

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ABOUT THE AUTHORS

V. Rajesh
Mr.V.Rajesh is pursuing his Master’s Degree in Embedded Systems Technology from SRM University, Chennai. He received B.E Degree (Electronics and Communication Engg.) from Anna University, Chennai in 2009.He is the student member of IEEE, ISTE. His current research interests include System on Chip design, embedded systems, Real Time Systems and wireless sensor Network communication.

P. Vijaya Kumar
Mr.P.Vijaya kumar is working as Asst. Professor (Sr.G) in department of ECE, SRM University. He received his M.tech (Applied Electronics) from College of Engineering, Guindy, Anna University, Chennai and B.E (Electronics and communication engg.) from Madras University, Chennai. His research area of interest is Intelligent Signal Processing, Wireless Sensor Networks and Real time computation in SOC. He is life time member of IACSIT, IAENG, ISC, ACEEE and ACM.


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