Friday 29th of March 2024
 

Area Efficient Design of Routing Node for Network-on-Chip



Network-on-Chip (NoC) is a paradigm proposed to satisfy the communication demands of future Systems-on-Chip (SoC). The main components of an NoC are the network adapters, routing nodes, and network interconnect links. Reducing area and power consumption has higher priority in the case of on-chip networks compared to conventional off-chip networks. This paper presents an area efficient design for the routing node component of an NoC. The area efficiency is obtained by applying the concept of a pipelined design as well as the use of custom IP (intellectual property) cores.

Keywords: Network-on-Chip (NoC), router, crossbar switch, virtual output queuing, ASIC (application specific integrated circuit) implementation

Download Full-Text

IJCSI Published Papers Indexed By:

 

 

 

 
+++
About IJCSI

IJCSI is a refereed open access international journal for scientific papers dealing in all areas of computer science research...

Learn more »
Join Us
FAQs

Read the most frequently asked questions about IJCSI.

Frequently Asked Questions (FAQs) »
Get in touch

Phone: +230 911 5482
Email: info@ijcsi.org

More contact details »