A Proficient Design of Hybrid Synchronous and Asynchronous Digital FIR Filter using FPGA
In this paper, a hybrid synchronous and asynchronous digital FIR filter is designed and implemented in FPGA using VHDL. The digital FIR filter of high throughput, low latency operating at above 1.3 GHz was designed. An adaptive high capacity pipelined was introduced in the hybrid synchronous asynchronous design of the filter. The degree of the pipelining is dynamically variable depending upon the input. Concurrent execution of software or program can be achieved in FPGA through parallel processing. The designed digital FIR filter is simulated using ModelSim and implemented using Xilinx. The simulation results are presented for different order such as 3, 6 and 15. The FIR filter designed is synthesized in Xilinx 9.1i and the device utilization report is presented for filter of order 3, 6 and 15.
Keywords: FPGA, Asynchronous pipeline, dynamic logic, FIR Filter
Download Full-Text
ABOUT THE AUTHORS
B.Paulchamy
Asst Professor,Department Of ECE, Hindusthan Institute of Technology Coimbatore-32
Ila Vennila
Associate professor, Department Of EEE PSG College of Technology Coimbatore-04
B.Paulchamy
Asst Professor,Department Of ECE, Hindusthan Institute of Technology Coimbatore-32
Ila Vennila
Associate professor, Department Of EEE PSG College of Technology Coimbatore-04
