A New Routing Algorithm for a Three-Stage Clos Interconnection Networks
Clos Interconnection network is one of the known connection networks in processing systems and distributed systems, which is used extensively in many fields such as Telecommunication networks, ATM switches and Data transmission. In order to eliminate the blocking in such networks, various routing algorithm have been proposed, each imposing extra costs due to hardware use and re-routing algorithm. This study offers a routing algorithm which takes a blocking-avoidance approach hence avoiding related costs. There is no blocking while the primary routing is performed from the input to output. This method has the complexity of O(NN). The results show that this algorithm is simpler than the algorithms previously proposed.
Keywords: Clos Interconnection Networks, Routing Algorithm, Blocking Avoidance, Three Stage Interconnection Networks.
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ABOUT THE AUTHORS
Zahra Sadat Ghandriz
Zahra Sadat Ghandriz was born in Yazd, Iran. She is currently a Master student in Hardware Engineering at Azad University of Qazvin, Iran. She received her B.Sc. degree in Software Engineering from Azad University, Maybod, Iran. Her research interests include Parallel Processing in Interconnection Networks and Parallel Algorithms.
Esmaeil Zeinali Khasraghi
Esmaeil Zeinali Khasraghi earned his B.Sc. degree in Computer Engineering (Software) from Qazvin Islamic Azad University (QIAU), and his M.Sc. and PhD degrees in Computer Engineering (Computer Architecture and Hardware) from Science and Research University, Tehran, Iran. He is an Assistant Professor of computer engineering and the QIAU Vice-President for Education since 2004. Working as a full-time faculty member of QIAU, he also directs the High Performance Computing and Networking Research Labs at the university. His research interests include Parallel and Distributed Systems, Optical and Wireless Networks and High Performance Computer Architecture.
Zahra Sadat Ghandriz
Zahra Sadat Ghandriz was born in Yazd, Iran. She is currently a Master student in Hardware Engineering at Azad University of Qazvin, Iran. She received her B.Sc. degree in Software Engineering from Azad University, Maybod, Iran. Her research interests include Parallel Processing in Interconnection Networks and Parallel Algorithms.
Esmaeil Zeinali Khasraghi
Esmaeil Zeinali Khasraghi earned his B.Sc. degree in Computer Engineering (Software) from Qazvin Islamic Azad University (QIAU), and his M.Sc. and PhD degrees in Computer Engineering (Computer Architecture and Hardware) from Science and Research University, Tehran, Iran. He is an Assistant Professor of computer engineering and the QIAU Vice-President for Education since 2004. Working as a full-time faculty member of QIAU, he also directs the High Performance Computing and Networking Research Labs at the university. His research interests include Parallel and Distributed Systems, Optical and Wireless Networks and High Performance Computer Architecture.
