A High Performance Architecture for 3D Wavelet Transform
Discrete Wavelet Transform (DWT) is attracted great deal of attention and used in various image, video and signal processing applications. Even though lifting scheme is proposed to reduce the computational load of DWT, traditional hardware solutions based on lifting scheme for DWT suffer from high critical path and computational resources. Flipping structure has been proposed to resolve these problems in the lifting based hardware implementations for DWT. In this paper we propose a pipeline architecture based on flipping structure for 3D DWT. The proposed architecture has lower critical path and computational resources compared to the other proposed hardwares for 3D DWT in the literature. Moreover, the proposed architecture can be used to implement 1D and 2D DWT besides the 3D DWT.
Keywords: 3D Wavelet Transform, Computational resources, Critical path, Flipping Scheme, Lifting Scheme
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ABOUT THE AUTHORS
Zahra Zaremojtahedi
received the B.Sc. degree in computer engineering from computer engineering department of Central Tehran branch of Iran Islamic Azad University. She is currently the M.Sc. student in the computer engineering department of Science and Research branch of Iran Islamic Azad University, Tehran, Iran. Her research interests include hardware design for image and video coding algorithms.
Farzad Zargari
received his B.Sc. degree in Electrical Engineering from Sharif University of Technology and his M.Sc. and Ph.D. degrees in Electrical Engineering from University of Tehran, all in Tehran, Iran. He is currently a research associate at the information technology department of research institute for ICT, formerly known as Iran Telecom Research Center (ITRC), Ministry of Telecommunications and Information Technology of Iran. He is also a teaching academic staff in the computer engineering department of Science and Research branch of Islamic Azad University. His research interests include multimedia systems, image and video signal processing algorithms, and hardware implementation of image and video coding standards.
Zahra Zaremojtahedi
received the B.Sc. degree in computer engineering from computer engineering department of Central Tehran branch of Iran Islamic Azad University. She is currently the M.Sc. student in the computer engineering department of Science and Research branch of Iran Islamic Azad University, Tehran, Iran. Her research interests include hardware design for image and video coding algorithms.
Farzad Zargari
received his B.Sc. degree in Electrical Engineering from Sharif University of Technology and his M.Sc. and Ph.D. degrees in Electrical Engineering from University of Tehran, all in Tehran, Iran. He is currently a research associate at the information technology department of research institute for ICT, formerly known as Iran Telecom Research Center (ITRC), Ministry of Telecommunications and Information Technology of Iran. He is also a teaching academic staff in the computer engineering department of Science and Research branch of Islamic Azad University. His research interests include multimedia systems, image and video signal processing algorithms, and hardware implementation of image and video coding standards.
