A CDMA Based Scalable Hierarchical Architecture for Network-On-Chip
A Scalable hierarchical architecture based Code-Division Multiple Access (CDMA) is proposed for high performance Network-on-Chip (NoC). This hierarchical architecture provides the integration of a large number of IPs in a single on-chip system. The network encoding and decoding schemes for CDMA transmission are provided. The proposed CDMA NoC architecture is compared to the conventional architecture in terms of latency, area and power dissipation. The overall area required to implement the proposed CDMA NoC design is reduced by 24.2%. The design decreases the latency of the network by 40%. The total power consumption required to achieve the proposed design is also decreased by 25%.
Keywords: Scalable, CDMA, NoC, Hierarchical Architecture, Paper dissipation.
Download Full-Text
ABOUT THE AUTHORS
Ahmed A. El Badry
Received the B.S degree in Communication engineering from the German University in Cairo (GUC), Cairo, Egypt in 2012. His research interest is in Network on Chip design. He was the author of a paper based on his B.S project in 2012.
Mohamed A. Abd El Ghany
Received the B.S. degree in electronics and communications engineering (with honors) and the Masters degrees in electronics engineering from Cairo University, Cairo, Egypt, in 2000 and 2006, respectively, and Ph.D degree in the area of high-performance VLSI/IC design from the German University, Cairo, Egypt in 2010. From 2003 to 2006, he was in National Space Agency of Ukraine, EGYPTSAT-1 project. From 2008 to 2009, he was an International Scholar at the Ohio State University, Electrical Engineering Dept., Columbus, USA. He is currently working as a Lecturer in German University in Cairo, Egypt. His research interest is in Network on Chip design and related circuit level issues in high performance VLSI circuits, clock distribution network design, and low-power design. He is the author of about 20papers and two book chapters in the fields of high throughput and low-power NoC design.
Ahmed A. El Badry
Received the B.S degree in Communication engineering from the German University in Cairo (GUC), Cairo, Egypt in 2012. His research interest is in Network on Chip design. He was the author of a paper based on his B.S project in 2012.
Mohamed A. Abd El Ghany
Received the B.S. degree in electronics and communications engineering (with honors) and the Masters degrees in electronics engineering from Cairo University, Cairo, Egypt, in 2000 and 2006, respectively, and Ph.D degree in the area of high-performance VLSI/IC design from the German University, Cairo, Egypt in 2010. From 2003 to 2006, he was in National Space Agency of Ukraine, EGYPTSAT-1 project. From 2008 to 2009, he was an International Scholar at the Ohio State University, Electrical Engineering Dept., Columbus, USA. He is currently working as a Lecturer in German University in Cairo, Egypt. His research interest is in Network on Chip design and related circuit level issues in high performance VLSI circuits, clock distribution network design, and low-power design. He is the author of about 20papers and two book chapters in the fields of high throughput and low-power NoC design.
