A Technique to Reduce Transition Energy for Data-Bus in DSM Technology
As CMOS VLSI integration continues with shrinking feature
size, the energy dissipation on the on-chip data buses and long
interconnects becoming a bottle neck for high performance
integrated circuits. This energy dissipation is due to increase in
inter-wire capacitance. This capacitance on on-chip data buses
and long interconnects plays an important role in the reliability
and performance of the system. These on-chip data buses
consumes major portion of wiring energy. Hence this energy
dissipation can be reduced by encoding the data on the data bus.
Hence transition energy reduction data bus encoding scheme is
proposed which can reduce the energy dissipation on on-chip
data buses. The proposed technique can able to reduce the energy
dissipation by 42% to 47% for 8-bit, 16-bit, 32-bit and 64-bit
data buses compare with unencoded data and 1% to 26% more
compare with other existing techniques.
Keywords: CMOS, Inter-wire capacitance, VLSI, Feature size, Data bus, interconnects, energy dissipation
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