A Resolution for Shared Memory Conflict in Multiprocessor System-on-a-Chip
Now days, manufacturers are focusing on increasing
the concurrency in multiprocessor system-on-a-chip (MPSoC)
architecture instead of increasing clock speed, for embedded
systems. Traditionally lock-based synchronization is provided to
support concurrency; as managing locks can be very difficult and
error prone. Transactional memories and lock based systems
have been extensively used to provide synchronization between
multiple processors in general-purpose systems. It has been
shown that locks have numerous shortcomings over transactional
memory in terms of power consumption, ease of programming
and performance. In this paper, we propose a new semaphore
scheme for synchronization in shared cache memory in an
MPSoC. Moreover, we have evaluated and compared our scheme
with locks and transactions in terms of energy consumption and
cache miss rate using SimpleScalar functional simulator.
Keywords: Cache Coherence, Embedded Systems, Locks, Transactions
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